From Newsgroup: comp.arch

On Sat, 1 Mar 2025 08:09:35 -0000 (UTC), Lawrence D'Oliveiro
<[email protected]d> wrote:

The VAX project started roughly around the time the first RISC
concepts were being researched. Could the VAX have been designed as a
RISC architecture to begin with? Because not doing so meant that, just
over a decade later, RISC architectures took over the “real computer” >market and wiped the floor with DEC’s flagship architecture, >performance-wise.

The answer was no, the VAX could not have been done as a RISC
architecture. RISC wasn’t actually price-performance competitive until
the latter 1980s:

Shall we then conclude that DEC did everything right, because later on
after the VAX, DEC came up with the Alpha, which was RISC, and which
was the highest-performing chip of its day?

Well, not everything. The Alpha was so expensive as to be a dismal
failure in the market. However, it was either good enough, or
well-documented enough, for some Chinese efforts at home-grown
computer design to have copied it.

John Savard
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From Newsgroup: comp.arch

[email protected] (John Savard) posted:

/ERROR "unexpected byte sequence starting at index 348: '\xE2'" while decoding/:

On Sat, 1 Mar 2025 08:09:35 -0000 (UTC), Lawrence D'Oliveiro
<[email protected]d> wrote:

The VAX project started roughly around the time the first RISC
concepts were being researched.

I remember walking by a CS conference room 1973-ish and listening to
a bunch of people (including Bill Wolfe and Aho) at Carnegie Mellon.
The discussion was about a follow on to the PDP-11 architectures
and what additional address modes should go in or not.

So, my memory is that VAX was being fleshed out at least 7 years
before RISC got started.

Could the VAX have been designed as a

RISC architecture to begin with?

Not with the players involved. Now, if Thronton or Seymore was at CMU
then maybe.

Because not doing so meant that, just

over a decade later, RISC architectures took over the “real computer”
market and wiped the floor with DEC’s flagship architecture, >performance-wise.

The answer was no, the VAX could not have been done as a RISC
architecture. RISC wasn’t actually price-performance competitive until >the latter 1980s:

Once compilers made significant growth in optimization, and sufficient
silicon area became available.

Shall we then conclude that DEC did everything right, because later on
after the VAX, DEC came up with the Alpha, which was RISC, and which
was the highest-performing chip of its day?

The commercial success of VAX delayed Alpha--no doubt about that. So, I contend, DEC misplayed that card.

Well, not everything. The Alpha was so expensive as to be a dismal
failure in the market. However, it was either good enough, or
well-documented enough, for some Chinese efforts at home-grown
computer design to have copied it.

John Savard

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From Newsgroup: comp.arch

On 2026-10-24, MitchAlsup <[email protected]d> wrote:

[email protected] (John Savard) posted:

/ERROR "unexpected byte sequence starting at index 348: '\xE2'" while decoding/:

On Sat, 1 Mar 2025 08:09:35 -0000 (UTC), Lawrence D'Oliveiro
<[email protected]d> wrote:

The VAX project started roughly around the time the first RISC
concepts were being researched.

I remember walking by a CS conference room 1973-ish and listening to
a bunch of people (including Bill Wolfe and Aho) at Carnegie Mellon.
The discussion was about a follow on to the PDP-11 architectures
and what additional address modes should go in or not.

So, my memory is that VAX was being fleshed out at least 7 years
before RISC got started.

The 801 certainly counts, but it was certainly not mainstream at
the time.

Could the VAX have been designed as a

RISC architecture to begin with?

Not with the players involved. Now, if Thronton or Seymore was at CMU
then maybe.

Because not doing so meant that, just

over a decade later, RISC architectures took over the ??????real computer??????
market and wiped the floor with DEC??????s flagship architecture,
performance-wise.

The answer was no, the VAX could not have been done as a RISC
architecture. RISC wasn??????t actually price-performance competitive until >> >the latter 1980s:

Once compilers made significant growth in optimization, and sufficient silicon area became available.

Again, the 801 proved that it could be done. I think they also
invented graph coloring for register allocation, or if they did
not invent it, they certainly used it.
--
This USENET posting was made without artificial intelligence,
artificial impertinence, artificial arrogance, artificial stupidity,
artificial flavorings or artificial colorants.
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From Newsgroup: comp.arch

On Sat, 24 Oct 2026 19:28:02 GMT, MitchAlsup wrote:

The commercial success of VAX delayed Alpha--no doubt about that.
So, I contend, DEC misplayed that card.

But DEC did bring out their first Unix-based RISC product in 1989 --
the MIPS-based DECstation. But there was still internal feuding
between the “Unix Is Snake Oil” camp (led by Ken Olsen himself) and
the “Customers Want An Open OS” camp, which prevented the company committing wholesale to the latter viewpoint.

The holdouts were not completely neutralized until Ken Olsen’s time as
CEO came to an end.
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From Newsgroup: comp.arch

Lawrence =?iso-8859-13?q?D=FFOliveiro?= <[email protected]d> posted:

On Sat, 24 Oct 2026 19:28:02 GMT, MitchAlsup wrote:

The commercial success of VAX delayed Alpha--no doubt about that.
So, I contend, DEC misplayed that card.

But DEC did bring out their first Unix-based RISC product in 1989 --
the MIPS-based DECstation. But there was still internal feuding
between the “Unix Is Snake Oil” camp (led by Ken Olsen himself) and
the “Customers Want An Open OS” camp, which prevented the company committing wholesale to the latter viewpoint.

The holdouts were not completely neutralized until Ken Olsen’s time as
CEO came to an end.

Faced the same war at Motorola where the factory and 68K design team
(150+ people) waged war on 88K design team (22) with the same conclusion::

Moto is no longer in the CPU game.
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From Newsgroup: comp.arch

On 2026-Oct-24 15:28, MitchAlsup wrote:

[email protected] (John Savard) posted:

/ERROR "unexpected byte sequence starting at index 348: '\xE2'" while decoding/:

On Sat, 1 Mar 2025 08:09:35 -0000 (UTC), Lawrence D'Oliveiro
<[email protected]d> wrote:

The VAX project started roughly around the time the first RISC
concepts were being researched.

I remember walking by a CS conference room 1973-ish and listening to
a bunch of people (including Bill Wolfe and Aho) at Carnegie Mellon.
The discussion was about a follow on to the PDP-11 architectures
and what additional address modes should go in or not.

So, my memory is that VAX was being fleshed out at least 7 years
before RISC got started.

According to one of Gordon Bell's web pages
the VAX project was officially started on 1-Apr-1975.
The VAX 780 product was introduced in Oct 1977.

Recall my prior post of the article from Electronics about memory prices
circa 1973 being about 10 cents per byte (in 1973 cents) as that would
strongly influence any architecture and ISA design decisions.

Also in 1975 DEC introduced the LSI-11 product built from a 3 chip set
MCP-1600 from Western Digital in 7u NMOS process at 3.3MHz (300ns microcycle). https://simh.trailing-edge.com/semi/lsi11.html https://en.wikipedia.org/wiki/PDP-11#LSI-11_integrated_circuits https://en.wikipedia.org/wiki/MCP-1600

So circa 1975 DEC had access to NMOS chip technology similar to 8080
if they had chosen to use it for a risc-VAX.

RISC architecture to begin with?

Not with the players involved. Now, if Thronton or Seymore was at CMU
then maybe.

Because not doing so meant that, just

over a decade later, RISC architectures took over the “real computer”
market and wiped the floor with DEC’s flagship architecture,
performance-wise.

The answer was no, the VAX could not have been done as a RISC
architecture. RISC wasn’t actually price-performance competitive until >>> the latter 1980s:

I disagree. As I mentioned above, the 1975 price of memory would be a
strong consideration. Compared to a variable length ISA of 2.5 to 3 bytes average, a fixed length 4-byte ISA would waste 1 to 1.5 bytes per instruction. I believe one could build a variable length instruction fetch/parse using standard 1975 TTL parts that can sustain 1 clock per instruction at 5 MHz. After that, just keep the instructions simple like risc so they decode easily.

That gives one the compact instruction size similar to cisc,
with the uArch design simplicity a risc decode and execute,
and performance of a pipelined processor.

You need to also consider R&D cost and time to market.

- IIRC I read someplace that VAX-780 design cost 300 man-years over 3 years.

- Looking at Hennessy's project notes for the Stanford MIPS,
and filtering out tool developments costs,
MIPS-1 design cost about 2 engineers working for 6 months.

Once compilers made significant growth in optimization, and sufficient silicon area became available.

By 1982 DEC research showed that VAX compilers only used 50 to 60 of its
304 instructions and 3 or 4 of its address modes.
See "A Case Study of VAX-11 Instruction Set Usage For Compiler Execution", 1982.

So compilers were already emitting risc-ish code.

Shall we then conclude that DEC did everything right, because later on
after the VAX, DEC came up with the Alpha, which was RISC, and which
was the highest-performing chip of its day?

The commercial success of VAX delayed Alpha--no doubt about that. So, I contend, DEC misplayed that card.

During the 1980's DEC had multiple proposals and projects floating
around internally but failed to capitalize on any of them.

There was the risc-ish Titan project circa 1982.

Titan System Manual 1986 WRL-86-1 https://www.bitsavers.org/pdf/dec/tech_reports/WRL-86-1.pdf

"The Titan project was begun as the initial project of the Western Research Laboratory in April of 1982. The most obvious milestones were the following: Apr 1982 Project begins
Mar 1983 CPU logic simulation
Oct 1984 CPU executing with toy memory system
May 1985 CPU executing with real memory system
Jun 1985 I/O starts working
Dec 1985 Complete system with all I/O running Unix"

"The first implementation of Titan is in 100K ECL, with a 45 nanosecond cycle time
and 13 cycle cache miss penalty. The central processor has a four-stage pipeline
with a peak instruction issue rate of one per cycle. Due to cache misses and pipeline stalls, a new instruction is typically issued every 1.5 cycles."

There were internal proposals to switch to an internal risc engine:

VOR: VAX on a RISC.
Internal memo, Digital Systems Research Center, December 1984 https://bwlampson.site/35a-VOR/35a-VORAbstract.html

Ideas for a simple fast VAX.
Internal memo, Digital Systems Research Center, October 1985 https://bwlampson.site/35b-IdeasFastVAX/35b-IdeasFastVAXAbstract.html

DEC PRISM (Parallel Reduced Instruction Set Machine) was circa 1988 https://en.wikipedia.org/wiki/DEC_PRISM

Well, not everything. The Alpha was so expensive as to be a dismal
failure in the market. However, it was either good enough, or
well-documented enough, for some Chinese efforts at home-grown
computer design to have copied it.

John Savard

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From Newsgroup: comp.arch

According to EricP <[email protected]>:

Recall my prior post of the article from Electronics about memory prices >circa 1973 being about 10 cents per byte (in 1973 cents) as that would >strongly influence any architecture and ISA design decisions.

Yes, they guessed wrong about the trajectory of memory prices.

I think they also had an implicit assumption that ROM would always be
faster than RAM so the cost of interpreting microcode would be low.

And they totally missed that people would stop writing systems code in assembler
and switch to higher level languages like C or PL/S or BLISS or Burroughs Algol.
The IBM 801 project was going on at the same time, with the compiler and the computer developed together. The 801 was a RISC largely because that was the code that the PL.8 compiler generated.

I recall reading somwhere that when they wrote a S/360 code generator
for PL.8, its code ran much faster than the regular PL/I compilers because
it mostly used a RISC-ish subset of the 360 instruction set that ran fast.
--
Regards,
John Levine, [email protected], Primary Perpetrator of "The Internet for Dummies",
Please consider the environment before reading this e-mail. https://jl.ly
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